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1 10-bit and 12-bit, 1msps sar adcs ISL267440, isl267450a the ISL267440 and isl267450a are 10-bit and 12-bit, 1msps sampling sar-type adcs featuring excellent linearity over supply and temperature variations, whic h are drop-in compatible with the ad7440 and ad7450a. the robust, fully-differential input offers high impedance to minimize errors due to leakage currents, and the specified measur ement accuracy is maintained with input signals up to the supply rails. the reference accepts inputs from 0.1v to 2.2v for 3v operation and 0.1v to 3.5v for 5v operation, which provides design flexibility in a wide variety of applications. the ISL267440, isl267450a also feature up to 8kv human body model esd survivability. the serial digital interface is spi compatible and is easily interfaced to all popular fpgas and microcontrollers. power dissipation is 8.5mw at a sampling rate of 1msps, and just 5w between conversions utilizing auto power-down mode (with a 5v supply), making the ISL267440, isl267450a excelle nt solutions for remote industrial sensors and battery-powered instruments. the ISL267440, isl267450a are av ailable in an 8 lead msop package, and are specified for operation over the industrial temperature range (?40c to +85c). features ? drop-in compatible with ad7440, ad7450a ? differential input ? simple spi-compatible serial digital interface ? guaranteed no missing codes ? 1mhz sampling rate ? 3v or 5v operation ?low operating current - 1.25ma at 1msps with 3v supplies - 1.70ma at 1msps with 5v supplies ? power-down current between conversions: 1a ? excellent differential non-linearity ? low thd: -83db (typ) ? pb-free (rohs compliant) ? available in msop package applications ? remote data acquisition ? battery operated systems ? industrial process control ? energy measurement ? data acquisition systems ? pressure sensors ? flow controllers figure 1. block diagram figure 2. diff erential linearity error vs code serial interface vdd vref gnd vin+ vin ? sclk sdata cs dac dac sar logic vref -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1 . 0 0 1024 2048 3072 4096 code dnl (lsb) december 5, 2011 fn7708.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. www.datasheet.co.kr datasheet pdf - http://www..net/
ISL267440, isl267450a 2 fn7708.0 december 5, 2011 typical connection diagram pin configuration ISL267440, isl267450a (8 ld msop) top view + vref vin+ vin? gnd vdd sclk sdata cs ref p-p + + +3v/5v supply p/ c vref serial interface 10 f 0.1 f ref p-p vref 8 7 6 5 1 2 3 4 vin+ vin ? gnd vdd sclk sdata cs pin descriptions ISL267440, isl267450a description pin name pin number vdd 8 supply voltage, +2.7v to 5.25v. sclk 7 serial clock input. controls digital i/o timing and clocks the conversion. sdata 6 digital conversion output. cs 5 chip select input. generally controls the start of a conversion though not always the sampling signal. gnd 4 ground vin? 3 negative analog input. vin+ 2 positive analog input. vref 1 reference voltage. www.datasheet.co.kr datasheet pdf - http://www..net/
ISL267440, isl267450a 3 fn7708.0 december 5, 2011 ordering information part number (note 4) part marking v dd range (v) temp range (c) package pkg. dwg. # ISL267440iuz (note 3) 67440 2.7 to 5.25 -40c to +85c 8 ld msop m8.118 ISL267440iuz-t (notes 1, 3) 67440 2.7 to 5.25 -40c to +85c 8 ld msop m8.118 ISL267440iuz-t7a (notes 1, 3) 67440 2.7 to 5.25 -40c to +85c 8 ld msop m8.118 isl267450aiuz (note 3) 7450a 2.7 to 5.25 -40c to +85c 8 ld msop m8.118 isl267450aiuz -t (notes 1, 3) 7450a 2.7 to 5.25 -40c to +85c 8 ld msop m8.118 isl267450aiuz -t7a (notes 1, 3) 7450a 2.7 to 5.25 -40c to +85c 8 ld msop m8.118 coming soon ISL267440ihz-t (notes 1, 2) 7440 2.7 to 5.25 -40c to +85c 8 ld sot-23 p8.064 coming soon ISL267440ihz-t7a (notes 1, 2) 7440 2.7 to 5.25 -40c to +85c 8 ld sot-23 p8.064 coming soon isl267450aihz-t (notes 1, 2) 450a 2.7 to 5.25 -40c to +85c 8 ld sot-23 p8.064 coming soon isl267450aihz-t7a (notes 1, 2) 450a 2.7 to 5.25 -40c to +85c 8 ld sot-23 p8.064 notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets; molding compounds/die attach materials and nipdau plate -e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free sold ering operations. intersil pb-fr ee products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 3. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 4. for moisture sensitivity level (msl), please see device information page for ISL267440 or isl267450a . for more information on msl please see techbrief tb363 . www.datasheet.co.kr datasheet pdf - http://www..net/
ISL267440, isl267450a 4 fn7708.0 december 5, 2011 table of contents pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical performance characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 adc transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 voltage reference input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 power-down/standby modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 dynamic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 static mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 short cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 power vs throughput rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 serial digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 adjustable low-noise reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 grounding and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 package outline drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 www.datasheet.co.kr datasheet pdf - http://www..net/
ISL267440, isl267450a 5 fn7708.0 december 5, 2011 absolute maximum rating s thermal information any pin to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.0v analog input to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v digital i/o to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v digital input voltage to gnd . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v maximum current in to any pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . . . 8kv machine model (tested per jesd22-a115b) . . . . . . . . . . . . . . . . . 400v charged device model (tested per jesd22-c101e). . . . . . . . . . . . 1.5kv latch up (tested per jesd78c; class 2, level a) . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 8 ld msop package (notes 5, 6). . . . . . . . . 165 64 8 ld sot-23 package (notes 5, 6). . . . . . . . 135 99 operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 6. for jc , the ?case temp? location is taken at the package top center. electrical specifications v dd = +3.0v to +3.6v, f sclk = 18mhz, f s = 1msps, v ref = 2.0v; v dd = +4.75v to +5.25v, f sclk =18mhz, f s =1msps, v ref = 2.5v; v cm = v ref , unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter test conditions ISL267440 isl267450a units min (note 7) typ max (note 7) min (note 7) typ max (note 7) dynamic performance sinad signal-to (noise + distortion) ratio f in = 100khz v dd = +4.75v to +5.25v 61.0 61.6 70.0 71.4 db f in = 100khz v dd = +3.0v to +3.6v 60.7 61.5 68.5 70.5 thd total harmonic distortion f in = 100khz v dd = +4.75v to +5.25v -82 -74 -84 -76 db f in = 100khz v dd = +3.0v to +3.6v -80 -72 -84 -74 db sfdr spurious free dynamic range f in = 100khz v dd = +4.75v to +5.25v -82 -76 -87 -76 db f in = 100khz v dd = +3.0v to +3.6v -82 -74 -85 -74 db imd intermodulation distortion 2nd and 3rd order, f in =90khz, 110khz -92 -95 db tpd aperture delay 1 1 ns tpd aperture jitter 15 15 ps 3db full power bandwidth @ ?3db 15 15 mhz dc accuracy nresolution 10 12 bits inl integral nonlinearity -0.5 0.1 0.5 -1 0.4 1 lsb dnl differential nonlinearity guaranteed no missed codes to 12 bits (isl267450a) or 10 bits (ISL267440) -0.5 0.1 0.5 -0.95 0.3 0.95 lsb offset zero-code error zero volt differential input -2.5 0.2 2.5 -6 0.2 6 lsb gain positive gain error ref input range -1 0.1 1-2 0.1 2 lsb negative gain error -1 0.1 1-2 0.1 2 analog input (note 8) |ain| full-scale input span 2 x v ref vin+ - vin? vin+ - vin? v www.datasheet.co.kr datasheet pdf - http://www..net/
ISL267440, isl267450a 6 fn7708.0 december 5, 2011 vin+, vin? absolute input voltage range v cm = v ref vin+ v cm v ref /2 v cm v ref /2 vin? v cm v ref /2 v cm v ref /2 i leak input dc leakage current -1 1 -1 1 a c vin input capacitance track/hold mode 13/5 13/5 pf reference input ref ref input voltage range v dd = 3v (1% tolerance for specified performance) 2.0 2.0 v v dd = 5v (1% tolerance for specified performance) 2.5 2.5 v i leak dc leakage current -1 1 -1 1 a c ref ref input capacitance track/hold mode 21/18.5 21/18.5 pf logic inputs v ih input high voltage 2.4 2.4 v v il input low voltage 0.8 0.8 v i leak input leakage current -1 1 -1 1 a c in input capacitance 10 10 pf logic outputs v oh output high voltage i source = 200a v dd - 0.3 v dd - 0.3 v v ol output low voltage i sink = 200a 0.4 0.4 v i oz floating-state output current -1 1 -1 1 a c out floating-state output capacitance 10 10 pf output coding two?s complement conversion rate t conv conversion time f sclk = 18mhz 888 888 ns t acq acquisition time 200 200 ns f max throughput rate 1000 1000 ksps power requirements v dd positive supply voltage range 2.73.62.73.6 v 4.75 5.25 4.75 5.25 v i dd positive supply input current static 11 a dynamic 3v 1250 1250 a 5v 1700 1700 a power dissipation static mode v dd = 3v 33 w v dd = 5v 55 w dynamic v dd = 3v, f smpl =1msps 3.75 3.75 mw v dd = 5v, f smpl =1msps 8.50 8.50 mw notes: 7. compliance to datasheet limits is assured by one or more methods: produc tion test, characterization and/or design. 8. the absolute voltage app lied to each analog input must be between gnd and v dd to guarantee datasheet performance. electrical specifications v dd = +3.0v to +3.6v, f sclk = 18mhz, f s = 1msps, v ref = 2.0v; v dd = +4.75v to +5.25v, f sclk =18mhz, f s =1msps, v ref = 2.5v; v cm = v ref , unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test conditions ISL267440 isl267450a units min (note 7) typ max (note 7) min (note 7) typ max (note 7) www.datasheet.co.kr datasheet pdf - http://www..net/
ISL267440, isl267450a 7 fn7708.0 december 5, 2011 timing specifications limits established by characterizati on and are not production tested. v dd = 3.0v to 3.6v, f sclk =18mhz, f s =1msps, v ref = 2.0v; v dd = 4.75v to 5.25v, f sclk =18mhz, f s = 1msps, v ref =2.5v; v cm = v ref unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter test conditions min (note 7) typ max (note 7) units f sclk clock frequency 0.01 18 mhz t sclk clock period 55 ns t acq acquisition time 200 ns t conv conversion time 888 ns t csw cs pulse width 10 ns t css cs falling edge to s clk falling edge setup time 10 ns t cdv cs falling edge to sdata valid 20 ns t clkdv sclk falling edge to sdata valid 40 ns t sdh sclk falling edge to sdata hold 10 ns t sw sclk pulse width 0.4 x t sclk ns t disable sclk falling edge to sdata disable time (note 9) extrapolated back to true bus relinquish 10 35 ns t quiet quiet time before sample 60 ns note: 9. during characterization, t disable is measured from the release point with a 10pf load (see figure 4) and the equivalent timing using the ad7440/450a loading (25pf) is calculated. figure 3. serial interface timing diagram cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 csb sclk dout 18mhz = 55.5556ns period 1 d0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d0 d0 d0 msb bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 t/h to hold mode, dout valid t/h to sample mode dout tristate dout d0 d0 d0 d0 msb bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 ISL267440 data output isl267450a data output bit0 bit0 figure 4. equivalent load circuit output pin c l 10pf vdd 2.85k r l www.datasheet.co.kr datasheet pdf - http://www..net/
ISL267440, isl267450a 8 fn7708.0 december 5, 2011 typical performance characteristics figure 5. isl267450a sinad vs analog input frequency for various supply voltages figure 6. isl267450a dynamic performance with v dd = 5v figure 7. cmrr vs frequency for v dd = 5v figure 8. typical dnl for the isl267450a for v dd = 5v figure 9. psrr vs supply ripple frequency without supply decoupling figure 10. typical inl for the isl267450a for v dd = 5v 55 60 65 70 75 10 100 1k input frequency (khz) sinad (dbc) 2.7v 3.6v 4.75v 5.25v -140 -120 -100 -80 -60 -40 -20 0 0 100 200 300 400 500 frequency (khz) 8192-point fft f sample = 1msps f in = 95.2khz sinad = 72.0db thd = -91db sfdr = 93db amplitude (dbfs) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10k 100k 1k 10k frequency (hz) cmrr (db) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 1024 2048 3072 4096 code dnl (lsb) -120 -100 -80 -60 -40 -20 0 0 100 200 300 400 500 600 700 800 900 1000 frequency (khz) 250mvp-p sine wave on vdd no decoupling on vdd psrr (db) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 1024 2048 3072 4096 code inl (lsb) www.datasheet.co.kr datasheet pdf - http://www..net/
ISL267440, isl267450a 9 fn7708.0 december 5, 2011 figure 11. change in dnl vs vref for the isl267450a for v dd = 5v figure 12. change in inl vs vref for the isl267450a for v dd =3v figure 13. change in dnl vs. vref for the isl267450a for v dd =3v figure 14. change in offset error vs reference voltage for v dd = 5v and 3v for the isl267450a figure 15. change in inl vs vref for the isl267450a for v dd =5v figure 16. change in enob vs reference voltage for v dd = 5v and 3v for the isl267450a typical performance characteristics (continued) -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v ref (v) dnl (lsb) neg dnl pos dnl -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 inl (lsb) v ref (v) neg inl pos inl -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 v ref (v) dnl (lsb) neg dnl pos dnl -2 -1 0 1 2 3 4 5 6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 zero code error (lsb) v ref (v) 3v v dd 5v v dd -5 -4 -3 -2 -1 0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 inl (lsb) v ref (v) neg inl pos inl 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 0.00.51.01.52.02.53.03.5 enob (bits) v ref (v) 5v v dd 3v v dd www.datasheet.co.kr datasheet pdf - http://www..net/
ISL267440, isl267450a 10 fn7708.0 december 5, 2011 figure 17. histogram of 10, 000 conversions of a dc input for the isl267450a with v dd = 5v figure 18. typical dnl for the ISL267440 for v dd = 5v figure 19. ISL267440 dyna mic performance with v dd = 5v figure 20. typical inl for the ISL267440 for v dd = 5v typical performance characteristics (continued) 0 10k 20k 30k 40k 50k 60k 70k 2044 2045 2046 2047 2048 2049 2050 code 65,516 codes 10 codes 10 codes hits -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 256 512 768 1024 code dnl (lsb) -140 -120 -100 -80 -60 -40 -20 0 0 100 200 300 400 500 frequency (khz) amplitude (dbfs) 8192-point fft f sample = 1msps f in = 95.2khz sinad = 61.6db thd = -75db sfdr = 81db -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 2 5 6 5 1 2 7 6 8 1 0 2 4 code inl (lsb) www.datasheet.co.kr datasheet pdf - http://www..net/
ISL267440, isl267450a 11 fn7708.0 december 5, 2011 functional description the ISL267440, isl267450a are based on a successive approximation register (sar) architecture utilizing capacitive charge redistribution digital to analog converters (dacs). figure 21 shows a simplified representation of the converter. during the acquisition phase (acq) the differential input is stored on the sampling capacitors (cs). the comparator is in a balanced state since the switch across its inputs is closed. the signal is fully acquired after t acq has elapsed, and the switches then transition to the conversion phase (conv) so the stored voltage may be converted to digital format. the comparator will become unbalanced when the differential switch opens and the input switches transition (assuming that the stored voltage is not exactly at mid-scale). the comparator output reflects whether the stored voltage is above or below mid-scale, which sets the value of the msb. the sar logic then forces the capacitive dacs to adjust up or down by one quarter of full-scale by switching in binarily weighted capacitors. again, the comparator output reflects whether the stored voltage is above or below the new value, setting the value of the next lowest bit. this process repeats until all 12 bits have been resolved. an external clock must be applied to the sclock pin to generate a conversion result. the allowable frequency range for sclock is 10khz to 18mhz (556sps to 1msp s). serial output data is transmitted on the falling edge of sclock. the receiving device (fpga, dsp or microcontroller) ma y latch the data on the rising edge of sclock to maximize set-up and hold times. a stable, low-noise reference voltage must be applied to the vref pin to set the full-scale input range and common-mode voltage. see ?voltage reference input? on page 12 for more details. adc transfer function the output codi ng for the ISL267440, isl267450a is twos complement. the first code transi tion occurs at successive lsb values (i.e., 1 lsb, 2 lsb, and so on). the lsb size of the isl267450a is 2*vref / 4096, while the ls b size of the ISL267440 is 2*vref / 1024. the ideal transfer characteristic of the ISL267440, isl267450a is shown in figure 22. analog input the ISL267440, isl267450a feature a fully differential input with a nominal full-scale range equal to twice the applied vref voltage. each input swings vref v p-p , 180 out of phase from one another for a total differential input of 2*vref (refer to figure 23). differential signaling offers several benefits over a single-ended input, such as: ? doubling of the full-scale in put range (and therefore the dynamic range) ? improved even order harmonic distortion ? better noise immunity due to common mode rejection figure 24 shows the relationship between the reference voltage and the full-scale input range for two different values of vref. figure 21. sar adc arch itectural block diagram vin + vin ? vref acq conv acq acq conv conv dac dac sar logic c s c s figure 22. ideal transf er characteristics figure 23. differential input signaling 1lsb = 2 x ref/4096 100...000 100...001 100...010 111...111 000...000 000...001 011...110 011...111 adc code analog input (vin+ ? vin-) -ref + 1lsb +ref - 1lsb 0lsb ISL267440, isl267450a v cm v ref pp v ref pp vin + vin ? www.datasheet.co.kr datasheet pdf - http://www..net/
ISL267440, isl267450a 12 fn7708.0 december 5, 2011 note that there is a trade-off between vref and the allowable common mode input voltage (vcm). the full-scale input range is proportional to vref; therefore the vcm range must be limited for larger values of vref in order to keep the absolute maximum and minimum voltages on the vin+ and vin? pins within specification. figures 25 and 26 illustrate this relationship for 5v and 3v operation, respectively. the dashed lines show the theoretical vcm range based sole ly on keeping the vin+ and vin? pins within the supply ra ils. additional restrictions are imposed due to the required headroom of the input circuitry, resulting in practical limits shown by the shaded area. voltage reference input an external low-noise reference voltage must be applied to the vref pin to set the full-scale input range of the converter. the reference input accepts voltages ranging from 0.1v to 2.2v for 3v operation and 0.1v to 3.5v for 5v operation. the device is specified with a reference voltag e of 2.5v for 5v operation and 2.0v for 3v operation. this pin should be decoupled with a combination of a 1f electrolytic capacitor and a 0.1f ceramic capacitor on the pc board. since the full-scale input range is proportional to the applied vref, any noise or drift will appear as an error in the conversion result. a low-noise, low-drift reference, such as the isl2100x family, may be used to maximize system performance, as shown in figure 27. the vref pin typica lly draws 4a and the current is dependent upon the sampled voltage. this can result in a code-dependent error if there is ex cessive series resistance or the reference lacks sufficient load regulation; therefore, buffering may be necessary. power-down/standby modes the mode of operation of th e ISL267440, isl267450a is selected by controlling the logic state of the cs signal during a conversion. there are two possible modes of operation: dynamic mode or static mode. when cs is high (deasserted) the adc will be in static mode. conversely, when cs is low (asserted) the device will be in dynamic mode. there are no minimum or maximum number of sclock cycles required to enter static mode, which simplifies power management and allows the user to easily optimize power dissipation versus throughput for different application requirements. figure 24. relationship between vref and full-scale range figure 25. relationship between vref and vcm for v dd = 5v 3.0 5.0 2.0 1.0 4.0 vi n+ vi n? vcm 2.0v p-p vref = 2v 3.0 5.0 2.0 1.0 4.0 vi n+ vi n? vcm 2.5v p-p vref = 2. 5v t v t v 3.0 5.0 2.0 1.0 4.0 vref vcm 0.5 1.0 1.5 2.0 2.5 3.0 3.5 3.25v 1.75v 4.25v figure 26. relationship between vref and vcm for v dd = 3v figure 27. buffered voltage reference 1.5 2.0 1.0 0.5 vref vcm 0.25 0.50 0.75 1.00 2.5 2.00 1.25 1.50 1.75 2.5 1.0v 2.0v vref + isl21009-25 ISL267440, isl267450a vout 2.5v www.datasheet.co.kr datasheet pdf - http://www..net/
ISL267440, isl267450a 13 fn7708.0 december 5, 2011 dynamic mode this mode is entered when a co nversion result is desired by asserting cs . figure 28 shows the general diagram of operation in this mode. the conversion is initiated on the falling edge of cs , as described in ?serial digital in terface? on page 13. as soon as cs is brought high, the conversion will be terminated and sdata will go back into three-state. sixteen serial clock cycles are required to complete the conversion and access the complete conversion result. cs may idle high until the next conversion or idle low until sometime prior to the next conversion. once a data transfer is complete, i.e., when sdata has returned to three- state, another conversion can be initiated by again bringing cs low . static mode the ISL267440, isl267450a enter the power-saving static mode automatically any time cs is deasserted. it is not required that the user force a device into this mode following a conversion in order to optimize power consumption. short cycling in cases where a lower resolution conversion is acceptable, cs can be pulled high before 12 sclock falling edges have elapsed. this is referred to as short cyclin g, and it can be used to further optimize power dissipation. in this mode a lower resolution result will be acquired, but the adc will enter static mode sooner and exhibit a lower average power dissipation than if the complete conversion cycle were carried out. the acquisition time ( t acq ) requirement must be met for the next conversion to be valid. power-on reset the ISL267440, isl267450a performs a power-on reset when the supplies are first activated, which requires approximately 2.5ms to execute. after this is complete, a single dummy cycle must be executed in order to initialize the switched capacitor track and hold. a dummy cycle will take 1 s with an 18mhz sclock. once the dummy cycle is complete, the adc mode will be determined by the state of cs . at this point, switching between dynamic and static modes is controlled by cs with no delay required between states. power vs throughput rate the ISL267440, isl267450a provide reduced power consumption at lower conversion rates by automatically switching into a low-power mode after completing a conversion. the average power consumption of the adc decreases at lower throughput rates. figure 29 shows the typical power consumption over a wide range of throughput rates. serial digital interface conversion data is accessed with an spi-compatible serial interface. the interface consists of the data clock (sclock), serial data output (sdata), and chip select (cs ). a falling edge on the cs signal initiates a conversion by placing the part into the acquisition (acq) phase. after t acq has elapsed, the part enters the conversion (conv) phase and begins outputting the conversion result starting with a null bit followed by the most significant bit (msb) and ending with the least significant bit (lsb). the cs pin can be pulled high at this point to put the device into standby mode and reduce the power consumption. if cs is held low after the lsb bit has been output, the serial output enters a high impedance state. the ISL267440, isl267450a will remain in this state, dissipating typical dynamic power levels, until cs transitions high then low to initiate the next conversion. data format output data is encoded in two?s complement format as shown in table 1. the voltage levels in the table are idealized and don?t account for any gain/offset errors or noise. applications information adjustable low-noise reference figure 30 illustrates how a digitally controlled potentiometer (dcp) can be used in conjunctio n with a low-noise, low-drift reference to realize an adjustable input range with high system accuracy. the voltage reference output is connected to the high terminal of the dcp and the wiper terminal is buffered and figure 28. normal mode operation sclk sdata cs 10 1 16 null bit and conversion result figure 29. power consumption vs throughput rate table 1. two?s complement data formatting input voltage digital output ?full scale ?vref 1000 0000 0000 ?full scale + 1lsb ?vref+ 1lsb 1000 0000 0001 midscale 0 0000 0000 0000 +full scale ? 1lsb +vref? 1lsb 0111 1111 1110 +full scale +vref 0111 1111 1111 0.01 0.1 1 10 100 0 50 100 150 200 250 300 350 throughput (ksps) power (mw) v dd = 3v v dd = 5v www.datasheet.co.kr datasheet pdf - http://www..net/
ISL267440, isl267450a 14 fn7708.0 december 5, 2011 connected to the adc reference. buffering is required since the ISL267440, isl267450a reference input current will cause a voltage drop across the dcp element (100k from rh to rl), impacting accuracy and increasing temperature drift. terminology signal-to-(noise + dist ortion) ratio (sinad) this is the measured ratio of sign al-to-(noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency ( f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more le vels, the smaller the quantization noise. the theoretical signal-to-(n oise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: thus, for a 12-bit converter this is 74db, and for a 10-bit this is 62db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ISL267440, isl267450a, it is defined as: where v 1 i s the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second to the sixth harmonics. peak harmonic or spurious noise (sfdr) peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental (also referred to as spurious free dynamic range (sfdr)). normally, the va lue of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m and n = 0, 1, 2 or 3. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb ) and (fa ? fb), while the third order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ?2fb). the ISL267440, isl267450a is te sted using the ccif standard, where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fu ndamentals expressed in dbs. aperture delay this is the amount of time from the leading edge of the sampling clock until the adc actually takes the sample. aperture jitter this is the sample-to-sample variation in the effective point in time at which the actual sample is taken. full power bandwidth the full power bandwidth of an adc is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input. common-mode rejection ratio (cmrr) the common-mode rejection ratio is defined as the ratio of the power in the adc output at full-scal e frequency, f, to the power of a 250mv p-p sine wave applied to the common-mode voltage of vin+ and vin? of frequency fs: pf is the power at the frequency f in the adc output; pfs is the power at frequency fs in the adc output. integral nonlinearity (inl) this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity (dnl) this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. zero-code error this is the deviation of the midscale code transition (111...111 to 000...000) from the ideal vin+ ? vin? (i.e., 0 lsb). positive gain error this is the deviation of the last code transition (011...110 to 011...111) from the ideal vin+ ? vin? (i.e., +ref ? 1 lsb), after the zero code error has been adjusted out. negative gain error this is the deviation of the first code transition (100...000 to 100...001) from the ideal vin+ ? vi n? (i.e., ? ref + 1 lsb), after the zero code error has been adjusted out. figure 30. adjustable buffered voltage reference x9119 vref + rh rl rw isl21009-25 ISL267440, isl267450a vout 2.5v signal-to-(noise + distortion) 6.02 n 1.76 + () db = (eq. 1) (eq. 2) thd db () 20 v 2 2 v 3 2 v 4 2 v 5 2 v 6 2 ++++ v 1 2 ----------------------------------------------------------------------- - log = (eq. 3) cmrr db () 10 pfl pfs ? () log = www.datasheet.co.kr datasheet pdf - http://www..net/
ISL267440, isl267450a 15 fn7708.0 december 5, 2011 track and hold acquisition time the track and hold acquisition time is the minimum time required for the track and hold am plifier to remain in track mode for its output to reach and settle to within 0.5 lsb of the applied input signal. power supply rejection ratio (psrr) the power supply rejection ratio is defined as the ratio of the power in the adc output at full-scale frequency, f, to adc vdd supply of frequency f s . the frequency of this input varies from 1khz to 1mhz. pf is the power at frequency f in the adc output; pfs is the power at frequency f s in the adc output. application hints grounding and layout the printed circuit board that houses the ISL267440, isl267450a should be designed so that the analog and digital sections are separated and conf ined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch tech nique is generally best for ground planes since it gives the be st shielding. digital and analog ground planes should be joined in only one place, and the connection should be a star ground point established as close to the gnd pin on the ISL267440, isl267450a as possible. avoid running digital lines under the device, as this will couple noise onto the die. the analog ground plane should be allowed to run under the ISL267440, isl267450a to avoid noise coupling. the power supply lines to the device should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. avoid crossover of digital and anal og signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with f tantalum capacitors in parallel with 0.1 f capacitors to gnd. to achieve the best from these decoupling components, they must be placed as close as possible to the device. (eq. 4) psrr db () 10 pf pfs ? () log = www.datasheet.co.kr datasheet pdf - http://www..net/
ISL267440, isl267450a 16 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7708.0 december 5, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: ISL267440 , isl267450a to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change december 5, 2011 fn7708.0 initial release. www.datasheet.co.kr datasheet pdf - http://www..net/
ISL267440, isl267450a 17 fn7708.0 december 5, 2011 package outline drawing m8.118 8 lead mini small outline plastic package rev 4, 7/11 detail "x" side view 2 typical recommended land pattern top view pin# 1 id 0.25 - 0.36 detail "x" 0.10 0.05 (4.40) (3.00) (5.80) h c 1.10 max 0.09 - 0.20 33 gauge plane 0.25 0.95 ref 0.55 0.15 b 0.08 c a-b d 3.00.05 12 8 0.85010 seating plane a 0.65 bsc 3.00.05 4.90.15 (0.40) (1.40) (0.65) d 5 5 side view 1 dimensioning and tolerancing conform to jedec mo-187-aa plastic interlead protrusions of 0.15mm max per side are not dimensions in ( ) are for reference only. dimensions are measured at datum plane "h". plastic or metal protrusions of 0.15mm max per side are not dimensions are in millimeters. 3. 4. 5. 6. notes: 1. 2. and amsey14.5m-1994. included. included. 0.10 c m www.datasheet.co.kr datasheet pdf - http://www..net/

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